Some modern computers use what are known as caches, which are basically small blocks of memory distributed throughout the computer which allow data to be stored and returned faster than if a large, central memory is asked for the information. An example of such a cache is an instruction stream (I-stream) cache dedicated to holding a stream of instructions for ready access. These instructions are sent to a decoder (through an instruction buffer) which decodes the I-stream, and sequentially handles processing of the specifiers and then the execution of each instruction. Specifically, the decoder parses the op-codes and operands held in the instruction buffer, thereby creating an entry point microaddress for a micro-sequencer which steps through microprograms. These entry points begin the microcode execution of operand fetch or op-code execution routines. In addition, the decoder passes other signals which it generates from the I-stream to other devices, such as increment control to a program counter, and control signals to file address logic.
In the past, computers have waited until a data stream, which is data from a data cache is verified as good before using it. This, of course, slows the machine down while the verification process is going on. A faster approach which has been taken has been to use the data just before it is verified as good, and repeat it if bad. However, an even faster approach is to use pipelining, and backing up by use of microtraps which are defined below. Basically, the data is used a relatively long time before it is verified as good data, and a trap occurs if the data turns out to be bad, as explained in more detail below.
Pipelining of instructions is used in order to speed up a machine. In non-pipelined machines, a piece of data will completely pass through a series of operations before the next piece of data begins passing through the series. In a pipelined machine, the next piece of data follows closely behind the first piece of data in entering a series of operations. In this manner, the second operation in the series will be operating on the first piece of data while the first operation in the series will be operating on the second piece of data to enter the series and so on.
Although pipelining increases the speed of a machine, a problem occurs due to microtraps. A microtrap is an event which has not occurred properly in the machine, as detected by a parity bit, for example. The microtrap is related to an instruction which was issued some time ago. When a microtrap occurs, the machine must take care of this problem. Due to pipelining, a program will continue to run after an instruction which causes a microtrap has issued. The computer then issues a trap handler address to go to some part of a program which will handle the microtrap. Because the machine has continued operating after the instruction which caused the microtrap occurrence, it may not be in a proper state at the time of the issuance of the trap handler address. Therefore, the machine is backed up to the state it was in at the time of the microtrap occurrence. Hereafter, the term "trap" will be used for the term "microtrap" for the sake of convenience.
A number of instructions have occurred during the trap shadow, which is the time between the issuance of the instruction which caused the trap and issuance of the trap handler address. After the machine has been backed up and is set going forward through the program again, the instructions which fall within the trap shadow must be replayed. Of course, it is desired that this replaying be done as quickly as possible.